View 74F194_258077.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

INTEGRATED CIRCUITS
74F194 4-bit bidirectional universal shift register
Product specification IC15 Data Handbook 1989 Apr 04
Philips Semiconductors
Philips Semiconductors
Product specification
4-bit bidirectional universal shift register
74F194
FEATURES
* Shift right and shift left capability * Synchronous parallel and serial data transfer * Easily expanded for both serial and parallel operation * Asynchronous Master Reset * Hold (do nothing) mode
DESCRIPTION
The functional characteristics of the 74F194 4-Bit Bidirectional Shift Register are indicated in the Logic Diagram and Function Table. The register is fully synchronous, with all operations taking place in less than 9ns (typical) for 74F, making the device especially useful for implementing very high speed CPUs, or for memory buffer registers. The 74F194 design has special logic features which increase the range of application. The synchronous operation of the device is determined by two Mode Select inputs, S0 and S1. As shown in the Mode Select-Function Table, data can be entered and shifted from left to right (shift right, Q0Q1, etc.), or right to left (shift left, Q3Q2, etc.), or parallel data can be entered, loading all 4 bits of the register simultaneously. When both S0 and S1 are Low, existing data is retained in a hold (do nothing) mode. The first and last stages provide D-type Serial Data inputs (DSR, DSL) to allow multistage shift right or shift left data transfers without interfering with parallel load operation. Mode Select and data inputs on the 74F194 are edge-triggered, responding only to the Low-to-High transition of the Clock (CP). Therefore, the only timing restriction is that the Mode Select and selected data inputs must be stable one setup time prior to the Low-to-High transition of the clock pulse. Signals on the Mode Select, Parallel Data (D0-D3) and Serial Data (DSR, DSL) can change when the clock is in either state, provided only the recommended setup and hold times, with respect to the clock rising edge, are observed. The four Parallel Data inputs (D0-D3) are D-type inputs. Data appearing on (D0-D3) inputs when S0 and S1 are High is transferred to the Q0-Q3 outputs respectively, following the next Low-to-High transition of the clock. When Low, the asynchronous Master Reset (MR) overrides all other input conditions and forces the Q outputs Low.
PIN CONFIGURATION
MR DSR D0 D1 D2 D3 DSL GND 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VCC Q0 Q1 Q2 Q3 CP S1 S0
SF00167
TYPE 74F194
TYPICAL fMAX 150MHz
TYPICAL SUPPLY CURRENT (TOTAL) 33mA
ORDERING INFORMATION
DESCRIPTION 16-pin plastic DIP 16-pin plastic SO COMMERCIAL RANGE VCC = 5V 10%, Tamb = 0C to +70C N74F194N N74F194D PKG DWG # SOT38-4 SOT109-1
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
PINS D0-D3 DSR DSL S0, S1 CP MR Q0-Q3 DESCRIPTION Parallel data inputs Serial data input (Shift Right) Serial data input (Shift Left) Mode Select inputs Clock Pulse input (active rising edge) Asynchronous master Reset input (Active Low) Data outputs 74F (U.L.) HIGH/LOW 1.0/1.0 1.0/1.0 1.0/1.0 1.0/1.0 1.0/1.0 1.0/1.0 50/33 LOAD VALUE HIGH/LOW 20A/0.6mA 20A/0.6mA 20A/0.6mA 20A/0.6mA 20A/0.6mA 20A/0.6mA 1.0mA/20mA
NOTE: One (1.0) FAST unit load is defined as: 20A in the High state and 0.6mA in the Low state.
April 4, 1989
2
853-0354 96224
Philips Semiconductors
Product specification
4-bit bidirectional universal shift register
74F194
LOGIC SYMBOL
2 3 4 5 6 7
IEC/IEEE SYMBOL
1 9 DSR D0 D1 D2 D3 DSL 10 11 S0 S1 CP MR Q0 Q1 Q2 Q3 2 3 4 5 6 SRG8 R 0 1 C4 1 /2 M 0 3
9 10 11 1
1, 4D 3, 4D 3, 4D 3, 4D 3, 4D 2, 4D
15 14 13 12
VCC = Pin 24 GND = Pin 12
7 15 14 13 12
SF00168
SF00169
LOGIC DIAGRAM
S1 S0 DSL D3 10 9 7 6 S CP R Q3 12 Q3
RD
S D2 5 CP R
Q2
13
Q2
RD
S D1 4 CP R
Q1
14
Q1
RD
S D0 3 CP R DSR MR CP VCC = Pin 24 GND = Pin 12 2 1 11
Q0
15
Q0
RD
SF00170
April 4, 1989
3
Philips Semiconductors
Product specification
4-bit bidirectional universal shift register
74F194
FUNCTION TABLE
INPUTS CP X X MR L H H H H H H S1 X l h h l l h S0 X l l l h h h DSR X X X X l h X DSL X X l h X X X Dn X X X X X X dn Q0 L q0 q1 q1 L H d0 OUTPUTS OPERATING MODES Q1 L q1 q2 q2 q0 q0 d1 Q2 L q2 q3 q3 q1 q1 d2 Q3 L q3 L Shift left H q2 Shift right q2 d3 Parallel load Reset (clear) Hold (do nothing)
H = High voltage level h = High voltage level one setup time prior to Low-to-High clock transition L = Low voltage level l = Low voltage level one setup time prior to Low-to-High clock transition X = Don't care = Low-to-High clock transition dn(qn) = Lower case letters indicate the state of the referenced input (or output) one setup time prior to the Low-to-High clock transition.
ABSOLUTE MAXIMUM RATINGS
(Operation beyond the limits set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the operating free-air temperature range.) SYMBOL VCC VIN IIN VOUT IOUT Tamb Tstg Supply voltage Input voltage Input current Voltage applied to output in High output state Current applied to output in Low output state Operating free-air temperature range Storage temperature range PARAMETER RATING -0.5 to +7.0 -0.5 to +7.0 -30 to +5 -0.5 to VCC 40 0 to +70 -65 to +150 UNIT V V mA V mA C C
RECOMMENDED OPERATING CONDITIONS
LIMITS SYMBOL VCC VIH VIL IIK IOH IOL Tamb Supply voltage High-level input voltage Low-level input voltage Input clamp current High-level output current Low-level output current Operating free-air temperature range 0 PARAMETER MIN 4.5 2.0 0.8 -18 -1 20 +70 NOM 5.0 MAX 5.5 V V V mA mA mA C UNIT
April 4, 1989
4
Philips Semiconductors
Product specification
4-bit bidirectional universal shift register
74F194
DC ELECTRICAL CHARACTERISTICS
SYMBOL PARAMETER TEST CONDITIONS1 VCC = MIN, VIL = MAX VIH = MIN, IOH = MAX VCC = MIN, VIL = MAX VIH = MIN, IOL = MAX VCC = MIN, II = IIK VCC = MAX, VI = 7.0V VCC = MAX, VI = 2.7V VCC = MAX, VI = 0.5V VCC = MAX VCC = MAX -60 33 10%VCC 5%VCC 10%VCC 5%VCC LIMITS MIN 2.5 2.7 3.4 0.30 0.30 -0.73 0.50 0.50 -1.2 100 20 -0.6 -150 46 V V A A mA mA mA V TYP2 MAX UNIT
VO OH
High-level High level output voltage3
VO OL VIK II IIH IIL IOS ICC
Low-level Low level output voltage Input clamp voltage Input current at maximum input voltage High-level input current Low-level input current Short-circuit output current4 Supply current (total)5
NOTES: 1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type. 2. All typical values are at VCC = 5V, Tamb = 25C. 3. Output High state will change to Low stat if an external voltage of less than 0.0V is applied. 4. Not more than one output should be shorted at a time. For testing IOS, the use of high-speed test apparatus and/or sample-and-hold techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting of a High output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any sequence of parameter tests, IOS tests should be performed last. 5. With all outputs open, Di inputs grounded and a 4.5V applied to S0, S1, MR and the serial inputs, ICC is tested with a momentary ground, then 4.5V applied to CP.
AC ELECTRICAL CHARACTERISTICS
LIMITS SYMBOL PARAMETER TEST CONDITION VCC = +5.0V Tamb = +25C CL = 50pF, RL = 500 MIN fMAX tPLH tPHL tPHL Maximum clock frequency Propagation delay CP to Qn Propagation delay MR to Qn Waveform 1 Waveform 1 Waveform 2 105 3.5 3.5 4.5 TYP 150 5.2 5.5 8.6 7.0 7.0 12.0 MAX VCC = +5.0V 10% Tamb = 0C to +70C CL = 50pF, RL = 500 MIN 90 3.5 3.5 4.5 8.0 8.0 14.0 MAX MHz ns ns UNIT
AC SETUP REQUIREMENTS
LIMITS SYMBOL PARAMETER TEST CONDITION VCC = +5.0V Tamb = +25C CL = 50pF, RL = 500 MIN tS(H) tS(L) th(H) th(L) tS(H) tS(L) th(H) th(L) tW(H) tW(L) tREC Setup time, High or Low Dn, DSL, DSR to CP Hold time, High or Low Dn, DSL, DSR to CP Setup time, High or Low Sn to CP Hold time, High or Low Sn to CP CP Pulse width, High MR Pulse width, Low Recovery time, MR to CP Waveform 3 Waveform 3 Waveform 3 Waveform 3 Waveform 1 Waveform 2 Waveform 2 4.0 4.0 0 0 8.0 8.0 0 0 5.0 5.0 7.0 TYP MAX VCC = +5.0V 10% Tamb = 0C to +70C CL = 50pF, RL = 500 MIN 4.0 4.0 1.0 1.0 9.0 8.0 0 0 5.5 5.0 8.0 MAX ns ns ns ns ns ns ns UNIT
April 4, 1989
5
Philips Semiconductors
Product specification
4-bit bidirectional universal shift register
74F194
AC WAVEFORMS
For all waveforms, VM = 1.5V. The shaded areas indicate when the input is permitted to change for predictable output performance.
1/fMAX CP
MR
VM tw(L)
VM tREC VM
VM tw(H) tPHL
VM
VM CP tPLH tPHL
Qn
VM
VM
Qn
VM
SF00171
SF00158
Waveform 1. Propagation Delay, Clock Input to Output, Clock Pulse Width, and Maximum Clock Frequency
Waveform 2. Master Reset Pulse Width, Master Reset to Output Delay, and Master Reset to Clock Recovery Time
Dn, DSR, DSL S0, S1
VM ts(H)
VM th(H)
VM ts(L)
VM th(L)
CP
VM
VM
SF00172
Waveform 3. Setup and Hold Times
TIMING DIAGRAM
Typical Clear, Load, Shift-Right, Shift-Left and Inhibit Sequence
CP S0 S1 MR SERIAL DATA INPUTS DSR DSL D0 PARALLEL DATA INPUTS D1 D2 D3 Q0 Q1 OUTPUTS Q2 Q3 SHIFT RIGHT CLEAR LOAD SHIFT LEFT INHIBIT CLEAR H L H L
SF00173
April 4, 1989
6
Philips Semiconductors
Product specification
4-bit bidirectional universal shift register
74F194
TEST CIRCUIT AND WAVEFORMS
VCC NEGATIVE PULSE VIN PULSE GENERATOR RT D.U.T. VOUT 90% VM 10% tTHL (tf ) CL RL tw VM 10% tTLH (tr ) 0V 90% AMP (V)
tTLH (tr ) 90% POSITIVE PULSE VM 10% tw
tTHL (tf ) AMP (V) 90% VM 10% 0V
Test Circuit for Totem-Pole Outputs DEFINITIONS: RL = Load resistor; see AC ELECTRICAL CHARACTERISTICS for value. CL = Load capacitance includes jig and probe capacitance; see AC ELECTRICAL CHARACTERISTICS for value. RT = Termination resistance should be equal to ZOUT of pulse generators.
Input Pulse Definition INPUT PULSE REQUIREMENTS family amplitude VM 74F 3.0V 1.5V rep. rate 1MHz tw 500ns tTLH 2.5ns tTHL 2.5ns
SF00006
April 4, 1989
7
Philips Semiconductors
Product specification
4-bit bidirectional universal shift register
74F194
DIP16: plastic dual in-line package; 16 leads (300 mil)
SOT38-4
1989 Apr 04
8
Philips Semiconductors
Product specification
4-bit bidirectional universal shift register
74F194
SO16: plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
1989 Apr 04
9
Philips Semiconductors
Product specification
4-bit bidirectional universal shift register
74F194
Data sheet status
Data sheet status Objective specification Preliminary specification Product specification Product status Development Qualification Definition [1] This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product. This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product.
Production
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.
Disclaimers
Life support -- These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes -- Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088-3409 Telephone 800-234-7381 (c) Copyright Philips Electronics North America Corporation 1998 All rights reserved. Printed in U.S.A. print code Document order number: Date of release: 10-98 9397-750-05095
Philips Semiconductors
yyyy mmm dd 10

▲Up To Search▲

Price & Availability of 74F194

	To Download 74F194 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .